Visualization Companion GNU Radio Conf 2017 Paper PDF Viz URL

RFNoC SISO Processor via High-Level Synthesis

A visual tour of how a soft-input soft-output decoder kernel becomes an RFNoC FPGA block: trellis recursions, state-metric pressure, HLS tradeoffs, and the gap between synthesis feasibility and a full deployed SDR decoder.

streaming fabric probabilistic state resource pressure integration boundary

Core Question

Can Vivado HLS package a SISO kernel into a reusable RFNoC block?

Algorithmic Core

BCJR / MAP style forward-backward trellis recursion

System Context

Software-defined radio, FEC, CHDR packet streaming

Takeaway

Strong HLS case study, weaker proof of full RFNoC deployment

References

Guerrieri, 2017. RFNoC SISO Processor via HLS

Braun et al., 2016. RFNoC: RF Network-on-Chip

Berrou et al., 1993. Turbo Codes

Bahl et al., 1974. BCJR / MAP Decoding

Robertson et al., 1995. Log-MAP vs Max-Log-MAP

McEliece et al., 1998. Turbo Decoding as Belief Propagation

Forney and Costello, 2007. Channel Coding and Capacity

Sunderlin, 2017. Measured RFNoC Latency