RFNoC SISO Processor via High-Level Synthesis
May 6, 2026
This episode explores a 2017 EPFL paper on turning a soft-input soft-output decoder kernel into a reusable RFNoC FPGA block using Vivado HLS, with a focus on software-defined radio and forward error correction. It explains why SISO processing sits at the core of turbo decoding, walking through the BCJR/MAP decoding logic, trellis-based forward and backward recursions, and the hardware challenges created by state metrics, memory traffic, and iterative probabilistic updates. The discussion argues that the paper is more convincing as a case study in HLS-based FPGA block construction and RFNoC integration than as proof of a complete, production-ready decoder system. Listeners would find it interesting for its clear look at the tradeoff between modular FPGA design convenience and the stubborn algorithmic complexity that still demands careful hardware thinking.
Interactive Visualization: RFNoC SISO Processor via High-Level Synthesis
Sources:
1. RFNoC SISO Processor via High-Level Synthesis
https://www.epfl.ch/labs/lap/wp-content/uploads/2018/11/GuerrieriSep17_DesigningAnRfnocBlockImplementingASisoProcessorUsingHighLevelSynthesis_GNURC17.pdf
2. RFNoC: RF Network-on-Chip — Martin Braun, Jonathan Pendlum, Matt Ettus, 2016
https://scholar.google.com/scholar?q=RFNoC%3A+RF+Network-on-Chip
3. Designing a RFNoC Block implementing a SISO Processor using High-Level Synthesis — Andrea Guerrieri, 2017
https://scholar.google.com/scholar?q=Designing+a+RFNoC+Block+implementing+a+SISO+Processor+using+High-Level+Synthesis
4. Measured Latency Introduced by RF Network-on-Chip (RFNoC) Architecture — Joshua Sunderlin, 2017
https://scholar.google.com/scholar?q=Measured+Latency+Introduced+by+RF+Network-on-Chip+%28RFNoC%29+Architecture
5. Adventures in RFNoC: Lessons Learned From Developing a Real-Time Spectrum Sensing Block — Rylee G. Mattingly, Justin G. Metcalf, 2022
https://scholar.google.com/scholar?q=Adventures+in+RFNoC%3A+Lessons+Learned+From+Developing+a+Real-Time+Spectrum+Sensing+Block
6. The Software Radio Architecture — Joseph Mitola III, 1995
https://scholar.google.com/scholar?q=The+Software+Radio+Architecture
7. State of the art baseband DSP platforms for Software Defined Radio: A survey — Omer Anjum, Tapani Ahonen, Fabio Garzia, Jari Nurmi, Claudio Brunelli, Heikki Berg, 2011
https://scholar.google.com/scholar?q=State+of+the+art+baseband+DSP+platforms+for+Software+Defined+Radio%3A+A+survey
8. Sora: High-Performance Software Radio Using General-Purpose Multi-Core Processors — Kun Tan, He Liu, Jiansong Zhang, Yongguang Zhang, Ji Fang, Geoffrey M. Voelker, 2011
https://scholar.google.com/scholar?q=Sora%3A+High-Performance+Software+Radio+Using+General-Purpose+Multi-Core+Processors
9. OpenRadio: A Programmable Wireless Dataplane — Manu Bansal, Jeffrey Mehlman, Sachin Katti, Philip Levis, 2012
https://scholar.google.com/scholar?q=OpenRadio%3A+A+Programmable+Wireless+Dataplane
10. A Mathematical Theory of Communication — Claude E. Shannon, 1948
https://scholar.google.com/scholar?q=A+Mathematical+Theory+of+Communication
11. Low-Density Parity-Check Codes — Robert G. Gallager, 1962
https://scholar.google.com/scholar?q=Low-Density+Parity-Check+Codes
12. Design of Capacity-Approaching Irregular Low-Density Parity-Check Codes — Thomas J. Richardson, M. Amin Shokrollahi, Rudiger L. Urbanke, 2001
https://scholar.google.com/scholar?q=Design+of+Capacity-Approaching+Irregular+Low-Density+Parity-Check+Codes
13. Channel Coding: The Road to Channel Capacity — G. David Forney Jr., Daniel J. Costello Jr., 2007
https://scholar.google.com/scholar?q=Channel+Coding%3A+The+Road+to+Channel+Capacity
14. Near Shannon Limit Error-Correcting Coding and Decoding: Turbo-Codes — Claude Berrou, Alain Glavieux, Punya Thitimajshima, 1993
https://scholar.google.com/scholar?q=Near+Shannon+Limit+Error-Correcting+Coding+and+Decoding%3A+Turbo-Codes
15. A Comparison of Optimal and Sub-Optimal MAP Decoding Algorithms Operating in the Log Domain — Patrick Robertson, Emmanuelle Villebrun, Peter Hoher, 1995
https://scholar.google.com/scholar?q=A+Comparison+of+Optimal+and+Sub-Optimal+MAP+Decoding+Algorithms+Operating+in+the+Log+Domain
16. Turbo Decoding as an Instance of Pearl's "Belief Propagation" Algorithm — Robert J. McEliece, David J. C. MacKay, Jung-Fu Cheng, 1998
https://scholar.google.com/scholar?q=Turbo+Decoding+as+an+Instance+of+Pearl%27s+%22Belief+Propagation%22+Algorithm
17. A Survey of Three-Dimensional Turbo Codes and Recent Performance Enhancements — Dhouha Kbaier Ben Ismail, Catherine Douillard, Sylvie Kerouedan, 2013
https://scholar.google.com/scholar?q=A+Survey+of+Three-Dimensional+Turbo+Codes+and+Recent+Performance+Enhancements
18. Optimal Decoding of Linear Codes for Minimizing Symbol Error Rate — Lalit R. Bahl, John Cocke, Frederick Jelinek, Josef Raviv, 1974
https://scholar.google.com/scholar?q=Optimal+Decoding+of+Linear+Codes+for+Minimizing+Symbol+Error+Rate
19. From Low-Architectural Expertise up to High-Throughput Non-Binary LDPC Decoders: Optimization Guidelines Using High-Level Synthesis — Nithin George, Kimon Karras, David Novo, Vitor Silva, Paolo Ienne, Gabriel Falcao, 2015
https://scholar.google.com/scholar?q=From+Low-Architectural+Expertise+up+to+High-Throughput+Non-Binary+LDPC+Decoders%3A+Optimization+Guidelines+Using+High-Level+Synthesis
20. Turbo Decoder Architecture for Beyond-4G Applications — Cheng-Chi Wong, Hsie-Chia Chang, 2014
https://scholar.google.com/scholar?q=Turbo+Decoder+Architecture+for+Beyond-4G+Applications
21. A DSP Shared Is a DSP Earned: HLS Task-Level Multi-Pumping for High-Performance Low-Resource Designs — approx. recent FPGA/HLS architecture authors, 2023-2026
https://scholar.google.com/scholar?q=A+DSP+Shared+Is+a+DSP+Earned%3A+HLS+Task-Level+Multi-Pumping+for+High-Performance+Low-Resource+Designs
22. Making Acceleration More Amenable with Novel High-Level Synthesis Techniques for FPGAs — approx. recent FPGA/HLS systems authors, 2023-2026
https://scholar.google.com/scholar?q=Making+Acceleration+More+Amenable+with+Novel+High-Level+Synthesis+Techniques+for+FPGAs
23. High-Level Synthesis for FPGAs: A Hardware Engineer's Perspective — approx. recent survey/review authors, 2023-2026
https://scholar.google.com/scholar?q=High-Level+Synthesis+for+FPGAs%3A+A+Hardware+Engineer%27s+Perspective
24. Implementation of Cognitive Radio Based on SDR and FPGA: Methods, Architectures and Practical Applicability — approx. SDR/FPGA survey authors, recent
https://scholar.google.com/scholar?q=Implementation+of+Cognitive+Radio+Based+on+SDR+and+FPGA%3A+Methods%2C+Architectures+and+Practical+Applicability
25. StreamPU: A DSEL for High Throughput and Low Latency Software-Defined Radio on Multicore CPUs — approx. Cassagne and collaborators, recent
https://scholar.google.com/scholar?q=StreamPU%3A+A+DSEL+for+High+Throughput+and+Low+Latency+Software-Defined+Radio+on+Multicore+CPUs
26. Run-Time Reconfigurable Systems and Algorithms for RFSoC-Based Software Defined Radio Applications — approx. recent RFSoC/SDR authors, recent
https://scholar.google.com/scholar?q=Run-Time+Reconfigurable+Systems+and+Algorithms+for+RFSoC-Based+Software+Defined+Radio+Applications
27. DecodeX: Exploring and Benchmarking of LDPC Decoding Across CPU, GPU, and ASIC Platforms — approx. recent benchmarking authors, recent
https://scholar.google.com/scholar?q=DecodeX%3A+Exploring+and+Benchmarking+of+LDPC+Decoding+Across+CPU%2C+GPU%2C+and+ASIC+Platforms
28. High-Throughput Software-Defined LDPC Encoder and Decoder with x86-Based Data-Level Parallelism — approx. recent communications authors, recent
https://scholar.google.com/scholar?q=High-Throughput+Software-Defined+LDPC+Encoder+and+Decoder+with+x86-Based+Data-Level+Parallelism
Interactive Visualization: RFNoC SISO Processor via High-Level Synthesis
1. RFNoC SISO Processor via High-Level Synthesis
https://www.epfl.ch/labs/lap/wp-content/uploads/2018/11/GuerrieriSep17_DesigningAnRfnocBlockImplementingASisoProcessorUsingHighLevelSynthesis_GNURC17.pdf
2. RFNoC: RF Network-on-Chip — Martin Braun, Jonathan Pendlum, Matt Ettus, 2016
https://scholar.google.com/scholar?q=RFNoC%3A+RF+Network-on-Chip
3. Designing a RFNoC Block implementing a SISO Processor using High-Level Synthesis — Andrea Guerrieri, 2017
https://scholar.google.com/scholar?q=Designing+a+RFNoC+Block+implementing+a+SISO+Processor+using+High-Level+Synthesis
4. Measured Latency Introduced by RF Network-on-Chip (RFNoC) Architecture — Joshua Sunderlin, 2017
https://scholar.google.com/scholar?q=Measured+Latency+Introduced+by+RF+Network-on-Chip+%28RFNoC%29+Architecture
5. Adventures in RFNoC: Lessons Learned From Developing a Real-Time Spectrum Sensing Block — Rylee G. Mattingly, Justin G. Metcalf, 2022
https://scholar.google.com/scholar?q=Adventures+in+RFNoC%3A+Lessons+Learned+From+Developing+a+Real-Time+Spectrum+Sensing+Block
6. The Software Radio Architecture — Joseph Mitola III, 1995
https://scholar.google.com/scholar?q=The+Software+Radio+Architecture
7. State of the art baseband DSP platforms for Software Defined Radio: A survey — Omer Anjum, Tapani Ahonen, Fabio Garzia, Jari Nurmi, Claudio Brunelli, Heikki Berg, 2011
https://scholar.google.com/scholar?q=State+of+the+art+baseband+DSP+platforms+for+Software+Defined+Radio%3A+A+survey
8. Sora: High-Performance Software Radio Using General-Purpose Multi-Core Processors — Kun Tan, He Liu, Jiansong Zhang, Yongguang Zhang, Ji Fang, Geoffrey M. Voelker, 2011
https://scholar.google.com/scholar?q=Sora%3A+High-Performance+Software+Radio+Using+General-Purpose+Multi-Core+Processors
9. OpenRadio: A Programmable Wireless Dataplane — Manu Bansal, Jeffrey Mehlman, Sachin Katti, Philip Levis, 2012
https://scholar.google.com/scholar?q=OpenRadio%3A+A+Programmable+Wireless+Dataplane
10. A Mathematical Theory of Communication — Claude E. Shannon, 1948
https://scholar.google.com/scholar?q=A+Mathematical+Theory+of+Communication
11. Low-Density Parity-Check Codes — Robert G. Gallager, 1962
https://scholar.google.com/scholar?q=Low-Density+Parity-Check+Codes
12. Design of Capacity-Approaching Irregular Low-Density Parity-Check Codes — Thomas J. Richardson, M. Amin Shokrollahi, Rudiger L. Urbanke, 2001
https://scholar.google.com/scholar?q=Design+of+Capacity-Approaching+Irregular+Low-Density+Parity-Check+Codes
13. Channel Coding: The Road to Channel Capacity — G. David Forney Jr., Daniel J. Costello Jr., 2007
https://scholar.google.com/scholar?q=Channel+Coding%3A+The+Road+to+Channel+Capacity
14. Near Shannon Limit Error-Correcting Coding and Decoding: Turbo-Codes — Claude Berrou, Alain Glavieux, Punya Thitimajshima, 1993
https://scholar.google.com/scholar?q=Near+Shannon+Limit+Error-Correcting+Coding+and+Decoding%3A+Turbo-Codes
15. A Comparison of Optimal and Sub-Optimal MAP Decoding Algorithms Operating in the Log Domain — Patrick Robertson, Emmanuelle Villebrun, Peter Hoher, 1995
https://scholar.google.com/scholar?q=A+Comparison+of+Optimal+and+Sub-Optimal+MAP+Decoding+Algorithms+Operating+in+the+Log+Domain
16. Turbo Decoding as an Instance of Pearl's "Belief Propagation" Algorithm — Robert J. McEliece, David J. C. MacKay, Jung-Fu Cheng, 1998
https://scholar.google.com/scholar?q=Turbo+Decoding+as+an+Instance+of+Pearl%27s+%22Belief+Propagation%22+Algorithm
17. A Survey of Three-Dimensional Turbo Codes and Recent Performance Enhancements — Dhouha Kbaier Ben Ismail, Catherine Douillard, Sylvie Kerouedan, 2013
https://scholar.google.com/scholar?q=A+Survey+of+Three-Dimensional+Turbo+Codes+and+Recent+Performance+Enhancements
18. Optimal Decoding of Linear Codes for Minimizing Symbol Error Rate — Lalit R. Bahl, John Cocke, Frederick Jelinek, Josef Raviv, 1974
https://scholar.google.com/scholar?q=Optimal+Decoding+of+Linear+Codes+for+Minimizing+Symbol+Error+Rate
19. From Low-Architectural Expertise up to High-Throughput Non-Binary LDPC Decoders: Optimization Guidelines Using High-Level Synthesis — Nithin George, Kimon Karras, David Novo, Vitor Silva, Paolo Ienne, Gabriel Falcao, 2015
https://scholar.google.com/scholar?q=From+Low-Architectural+Expertise+up+to+High-Throughput+Non-Binary+LDPC+Decoders%3A+Optimization+Guidelines+Using+High-Level+Synthesis
20. Turbo Decoder Architecture for Beyond-4G Applications — Cheng-Chi Wong, Hsie-Chia Chang, 2014
https://scholar.google.com/scholar?q=Turbo+Decoder+Architecture+for+Beyond-4G+Applications
21. A DSP Shared Is a DSP Earned: HLS Task-Level Multi-Pumping for High-Performance Low-Resource Designs — approx. recent FPGA/HLS architecture authors, 2023-2026
https://scholar.google.com/scholar?q=A+DSP+Shared+Is+a+DSP+Earned%3A+HLS+Task-Level+Multi-Pumping+for+High-Performance+Low-Resource+Designs
22. Making Acceleration More Amenable with Novel High-Level Synthesis Techniques for FPGAs — approx. recent FPGA/HLS systems authors, 2023-2026
https://scholar.google.com/scholar?q=Making+Acceleration+More+Amenable+with+Novel+High-Level+Synthesis+Techniques+for+FPGAs
23. High-Level Synthesis for FPGAs: A Hardware Engineer's Perspective — approx. recent survey/review authors, 2023-2026
https://scholar.google.com/scholar?q=High-Level+Synthesis+for+FPGAs%3A+A+Hardware+Engineer%27s+Perspective
24. Implementation of Cognitive Radio Based on SDR and FPGA: Methods, Architectures and Practical Applicability — approx. SDR/FPGA survey authors, recent
https://scholar.google.com/scholar?q=Implementation+of+Cognitive+Radio+Based+on+SDR+and+FPGA%3A+Methods%2C+Architectures+and+Practical+Applicability
25. StreamPU: A DSEL for High Throughput and Low Latency Software-Defined Radio on Multicore CPUs — approx. Cassagne and collaborators, recent
https://scholar.google.com/scholar?q=StreamPU%3A+A+DSEL+for+High+Throughput+and+Low+Latency+Software-Defined+Radio+on+Multicore+CPUs
26. Run-Time Reconfigurable Systems and Algorithms for RFSoC-Based Software Defined Radio Applications — approx. recent RFSoC/SDR authors, recent
https://scholar.google.com/scholar?q=Run-Time+Reconfigurable+Systems+and+Algorithms+for+RFSoC-Based+Software+Defined+Radio+Applications
27. DecodeX: Exploring and Benchmarking of LDPC Decoding Across CPU, GPU, and ASIC Platforms — approx. recent benchmarking authors, recent
https://scholar.google.com/scholar?q=DecodeX%3A+Exploring+and+Benchmarking+of+LDPC+Decoding+Across+CPU%2C+GPU%2C+and+ASIC+Platforms
28. High-Throughput Software-Defined LDPC Encoder and Decoder with x86-Based Data-Level Parallelism — approx. recent communications authors, recent
https://scholar.google.com/scholar?q=High-Throughput+Software-Defined+LDPC+Encoder+and+Decoder+with+x86-Based+Data-Level+Parallelism
Interactive Visualization: RFNoC SISO Processor via High-Level Synthesis