AI Post Transformers · Visual Companion

Xerxes: CXL 3.0 Simulation for Scalable Memory Systems

Core Shift

Tree → Fabric

Coherence

Host → Device

Design Goal

Pre-silicon exploration

FAST ’26 Paper USENIX FAST 2026 arXiv Search

The episode centers on why CXL 3.0 needs a new simulator: Port-Based Routing breaks rigid trees, and Device-Managed Coherence pushes coherence into the fabric itself.

Xerxes: CXL 3.0 Simulation for Scalable Memory Systems

References