This episode examines "Redwood," a company technical report claiming an AI system took a two-architect spec to verified RTL for a spatial dataflow inference accelerator in under two weeks, with 95% coverage per block and a Qwen3-0.6B bring-up in week three. The hosts argue over whether the 14% first-silicon success statistic actually motivates the paper's single-spec approach, or whether handoffs between architecture, RTL, verification and kernels are the real schedule bottleneck. They explain why batch-size-one physical-AI inference is memory-bound rather than compute-bound, and walk through the tile design: RISC-V control core, matrix engine, vector engine, 512 KB scratchpad and a credit-based network-on-chip. Throughout, they separate the FPGA results measured on a Versal VPK180 from the Samsung 8 nm figures, which are projections. Those projections include the headline 1.75x throughput, 1.9x lower power and 3.4x performance-per-watt versus a Jetson Orin Nano, and the authors' claim of early recursive self-improvement. It's useful for listeners who want to judge AI-driven chip design claims by what was actually demonstrated.
Sources:
1. Redwood: A Frontier AI Accelerator Designed, Verified, and Deployed from Scratch in 2 Weeks by AI — Architect Labs, 2026
http://arxiv.org/abs/2608.264182. ChipNeMo: Domain-Adapted LLMs for Chip Design — Mingjie Liu et al. (NVIDIA), 2023
https://scholar.google.com/scholar?q=ChipNeMo%3A+Domain-Adapted+LLMs+for+Chip+Design3. Pushing the Limits of Machine Design: Automated CPU Design with AI — Shuyao Cheng et al., 2023
https://scholar.google.com/scholar?q=Pushing+the+Limits+of+Machine+Design%3A+Automated+CPU+Design+with+AI4. Chip-Chat: Challenges and Opportunities in Conversational Hardware Design — Jason Blocklove, Siddharth Garg, Ramesh Karri, Hammond Pearce, 2023
https://scholar.google.com/scholar?q=Chip-Chat%3A+Challenges+and+Opportunities+in+Conversational+Hardware+Design5. VerilogEval: Evaluating Large Language Models for Verilog Code Generation — Mingjie Liu, Nathaniel Pinckney, Brucek Khailany, Haoxing Ren, 2023
https://scholar.google.com/scholar?q=VerilogEval%3A+Evaluating+Large+Language+Models+for+Verilog+Code+Generation6. CVDP: Verilog Design Problems benchmark for RTL design and verification agents — Nathaniel Pinckney et al. (NVIDIA), 2025
https://scholar.google.com/scholar?q=CVDP%3A+Verilog+Design+Problems+benchmark+for+RTL+design+and+verification+agents7. FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware — Minwoo Kang et al., 2024
https://scholar.google.com/scholar?q=FVEval%3A+Understanding+Language+Model+Capabilities+in+Formal+Verification+of+Digital+Hardware8. Roofline: An Insightful Visual Performance Model for Multicore Architectures — Samuel Williams, Andrew Waterman, David Patterson, 2009
https://scholar.google.com/scholar?q=Roofline%3A+An+Insightful+Visual+Performance+Model+for+Multicore+Architectures9. FlightLLM: Efficient Large Language Model Inference with a Complete Mapping Flow on FPGAs — Shulin Zeng et al., 2024
https://scholar.google.com/scholar?q=FlightLLM%3A+Efficient+Large+Language+Model+Inference+with+a+Complete+Mapping+Flow+on+FPGAs10. MLPerf Power: Benchmarking the Energy Efficiency of Machine Learning Systems from Microwatts to Megawatts for Sustainable AI — Arya Tschand et al., 2024
https://scholar.google.com/scholar?q=MLPerf+Power%3A+Benchmarking+the+Energy+Efficiency+of+Machine+Learning+Systems+from+Microwatts+to+Megawatts+for+Sustainable+AI11. An Empirical Study of Qwen3 Quantization — Xingyu Zheng et al., 2025
https://scholar.google.com/scholar?q=An+Empirical+Study+of+Qwen3+Quantization12. SmoothQuant: Accurate and Efficient Post-Training Quantization for Large Language Models — Guangxuan Xiao et al., 2023
https://scholar.google.com/scholar?q=SmoothQuant%3A+Accurate+and+Efficient+Post-Training+Quantization+for+Large+Language+Models13. AlphaEvolve: A coding agent for scientific and algorithmic discovery — Google DeepMind (Novikov et al.), 2025
https://scholar.google.com/scholar?q=AlphaEvolve%3A+A+coding+agent+for+scientific+and+algorithmic+discovery14. KernelBench: Can LLMs Write Efficient GPU Kernels? — Anne Ouyang et al., 2025
https://scholar.google.com/scholar?q=KernelBench%3A+Can+LLMs+Write+Efficient+GPU+Kernels%3F15. A graph placement methodology for fast chip design (and the follow-up critique 'Reevaluating Google's Reinforcement Learning for IC Macro Placement') — Azalia Mirhoseini et al. (2021); Igor Markov (2024), 2021/2024
https://scholar.google.com/scholar?q=A+graph+placement+methodology+for+fast+chip+design+%28and+the+follow-up+critique+%27Reevaluating+Google%27s+Reinforcement+Learning+for+IC+Macro+Placement%27%2916. Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration — Hasan Genc et al., 2021
https://scholar.google.com/scholar?q=Gemmini%3A+Enabling+Systematic+Deep-Learning+Architecture+Evaluation+via+Full-Stack+Integration