Machine Learning Self-Calibrated FPGA Time-to-Digital Converter
May 8, 2026
This episode explores an FPGA-based time-to-digital converter that combines careful delay-line layout with machine-learning-based calibration to achieve very fine timing measurements on real hardware. It explains how tapped-delay-line TDCs work, why real FPGA implementations suffer from nonuniform time bins and bubble errors, and why those imperfections matter for applications like LiDAR, medical imaging, particle physics, and high-speed communications. The discussion compares the new approach against earlier FPGA TDC work, arguing that the real contribution is not flashy AI but a practical learned decoder that maps a 940-bit raw hardware output into a more accurate time estimate after physical design has reduced as much noise as possible. Listeners would find it interesting because it gets specific about where machine learning genuinely helps in instrumentation: not replacing physics, but reducing calibration effort while preserving picosecond-level precision.
Interactive Visualization: Machine Learning Self-Calibrated FPGA Time-to-Digital Converter
Sources:
1. Machine Learning Self-Calibrated FPGA Time-to-Digital Converter
https://podcast.do-not-panic.com/uploaded-pdfs/2026-05-08T03-07-35-153Z-1-s2.0-S2667305326000190-main.pdf
2. A 19.6 ps, FPGA-Based TDC With Multiple Channels for Open Source Applications — Matthew W. Fishburn, L. Harmen Menninga, Claudio Favi, Edoardo Charbon, 2013
https://scholar.google.com/scholar?q=A+19.6+ps%2C+FPGA-Based+TDC+With+Multiple+Channels+for+Open+Source+Applications
3. A low nonlinearity, missing-code free time-to-digital converter based on 28nm FPGAs with embedded bin-width calibrations — Haochang Chen, Yongliang Zhang, David Day-Uei Li, 2017
https://scholar.google.com/scholar?q=A+low+nonlinearity%2C+missing-code+free+time-to-digital+converter+based+on+28nm+FPGAs+with+embedded+bin-width+calibrations
4. A 19 ps Precision and 170 M Samples/s Time-to-Digital Converter Implemented in FPGA with Online Calibration — Mengdi Zhang, Ye Zhao, Zhengsheng Han, Fazhan Zhao, 2022
https://scholar.google.com/scholar?q=A+19+ps+Precision+and+170+M+Samples%2Fs+Time-to-Digital+Converter+Implemented+in+FPGA+with+Online+Calibration
5. Low-Resource Time-to-Digital Converters for Field Programmable Gate Arrays: A Review — Diego Real, David Calvo, 2024
https://scholar.google.com/scholar?q=Low-Resource+Time-to-Digital+Converters+for+Field+Programmable+Gate+Arrays%3A+A+Review
6. Calibration Methods for Time-to-Digital Converters — Wassim Khaddour, Wilfried Uhring, Foudil Dadouche, Norbert Dumas, Morgan Madec, 2023
https://scholar.google.com/scholar?q=Calibration+Methods+for+Time-to-Digital+Converters
7. Time Resolution Improvement Using Dual Delay Lines for Field-Programmable-Gate-Array-Based Time-to-Digital Converters with Real-Time Calibration — Yuan-Ho Chen, 2019
https://scholar.google.com/scholar?q=Time+Resolution+Improvement+Using+Dual+Delay+Lines+for+Field-Programmable-Gate-Array-Based+Time-to-Digital+Converters+with+Real-Time+Calibration
8. Novel machine learning-driven optimizing decoding solutions for FPGA-based time-to-digital converters — Fabio Garzetti, Nicola Lusardi, Enrico Ronconi, Andrea Costa, Angelo Geraci, 2024
https://scholar.google.com/scholar?q=Novel+machine+learning-driven+optimizing+decoding+solutions+for+FPGA-based+time-to-digital+converters
9. A novel FPGA-based time-to-digital converter featuring machine learning-aided self-calibration — Arash Amini Bardpareh, Eleonora Vacca, Davide Nicolini, Corrado De Sio, Sarah Azimi, Luca Sterpone, Elisa Fiorina, Emanuele Maria Data, Felix Mas Milian, 2026
https://scholar.google.com/scholar?q=A+novel+FPGA-based+time-to-digital+converter+featuring+machine+learning-aided+self-calibration
10. Multiple-tapped-delay-line hardware-linearisation technique based on wire load regulation — Dariusz Chaberski, Robert Frankowski, Marek Zielinski, Lukasz Zaworski, 2016
https://scholar.google.com/scholar?q=Multiple-tapped-delay-line+hardware-linearisation+technique+based+on+wire+load+regulation
11. 5.7 ps Resolution Time-to-Digital Converter Implementation Using Routing Path Delays — Roza Teklehaimanot Siecha, Getachew Alemu, Jeffrey Prinzie, Paul Leroux, 2023
https://scholar.google.com/scholar?q=5.7+ps+Resolution+Time-to-Digital+Converter+Implementation+Using+Routing+Path+Delays
12. Tapped delay line for compact time-to-digital converter on UltraScale FPGA and its coding method — Min Zhu, Xihan Qi, Tang Cui, Qiang Gao, 2023
https://scholar.google.com/scholar?q=Tapped+delay+line+for+compact+time-to-digital+converter+on+UltraScale+FPGA+and+its+coding+method
13. A High-Resolution (Machine Learning Self-Calibrated FPGA Time-to-Digital Converter
1. Machine Learning Self-Calibrated FPGA Time-to-Digital Converter
https://podcast.do-not-panic.com/uploaded-pdfs/2026-05-08T03-07-35-153Z-1-s2.0-S2667305326000190-main.pdf
2. A 19.6 ps, FPGA-Based TDC With Multiple Channels for Open Source Applications — Matthew W. Fishburn, L. Harmen Menninga, Claudio Favi, Edoardo Charbon, 2013
https://scholar.google.com/scholar?q=A+19.6+ps%2C+FPGA-Based+TDC+With+Multiple+Channels+for+Open+Source+Applications
3. A low nonlinearity, missing-code free time-to-digital converter based on 28nm FPGAs with embedded bin-width calibrations — Haochang Chen, Yongliang Zhang, David Day-Uei Li, 2017
https://scholar.google.com/scholar?q=A+low+nonlinearity%2C+missing-code+free+time-to-digital+converter+based+on+28nm+FPGAs+with+embedded+bin-width+calibrations
4. A 19 ps Precision and 170 M Samples/s Time-to-Digital Converter Implemented in FPGA with Online Calibration — Mengdi Zhang, Ye Zhao, Zhengsheng Han, Fazhan Zhao, 2022
https://scholar.google.com/scholar?q=A+19+ps+Precision+and+170+M+Samples%2Fs+Time-to-Digital+Converter+Implemented+in+FPGA+with+Online+Calibration
5. Low-Resource Time-to-Digital Converters for Field Programmable Gate Arrays: A Review — Diego Real, David Calvo, 2024
https://scholar.google.com/scholar?q=Low-Resource+Time-to-Digital+Converters+for+Field+Programmable+Gate+Arrays%3A+A+Review
6. Calibration Methods for Time-to-Digital Converters — Wassim Khaddour, Wilfried Uhring, Foudil Dadouche, Norbert Dumas, Morgan Madec, 2023
https://scholar.google.com/scholar?q=Calibration+Methods+for+Time-to-Digital+Converters
7. Time Resolution Improvement Using Dual Delay Lines for Field-Programmable-Gate-Array-Based Time-to-Digital Converters with Real-Time Calibration — Yuan-Ho Chen, 2019
https://scholar.google.com/scholar?q=Time+Resolution+Improvement+Using+Dual+Delay+Lines+for+Field-Programmable-Gate-Array-Based+Time-to-Digital+Converters+with+Real-Time+Calibration
8. Novel machine learning-driven optimizing decoding solutions for FPGA-based time-to-digital converters — Fabio Garzetti, Nicola Lusardi, Enrico Ronconi, Andrea Costa, Angelo Geraci, 2024
https://scholar.google.com/scholar?q=Novel+machine+learning-driven+optimizing+decoding+solutions+for+FPGA-based+time-to-digital+converters
9. A novel FPGA-based time-to-digital converter featuring machine learning-aided self-calibration — Arash Amini Bardpareh, Eleonora Vacca, Davide Nicolini, Corrado De Sio, Sarah Azimi, Luca Sterpone, Elisa Fiorina, Emanuele Maria Data, Felix Mas Milian, 2026
https://scholar.google.com/scholar?q=A+novel+FPGA-based+time-to-digital+converter+featuring+machine+learning-aided+self-calibration
10. Multiple-tapped-delay-line hardware-linearisation technique based on wire load regulation — Dariusz Chaberski, Robert Frankowski, Marek Zielinski, Lukasz Zaworski, 2016
https://scholar.google.com/scholar?q=Multiple-tapped-delay-line+hardware-linearisation+technique+based+on+wire+load+regulation
11. 5.7 ps Resolution Time-to-Digital Converter Implementation Using Routing Path Delays — Roza Teklehaimanot Siecha, Getachew Alemu, Jeffrey Prinzie, Paul Leroux, 2023
https://scholar.google.com/scholar?q=5.7+ps+Resolution+Time-to-Digital+Converter+Implementation+Using+Routing+Path+Delays
12. Tapped delay line for compact time-to-digital converter on UltraScale FPGA and its coding method — Min Zhu, Xihan Qi, Tang Cui, Qiang Gao, 2023
https://scholar.google.com/scholar?q=Tapped+delay+line+for+compact+time-to-digital+converter+on+UltraScale+FPGA+and+its+coding+method
13. A High-Resolution (Machine Learning Self-Calibrated FPGA Time-to-Digital Converter