Agentic Hardware Design: Evolving RTL Through Repository-Level Code Loops

This episode examines HORIZON, a system from NVIDIA researchers (Cunxi Yu and colleagues) that treats RTL hardware design as repository-level code evolution, wrapping generation in a git-native loop where an LLM agent edits Verilog, an automated evaluator compiles and simulates each candidate, and only passing changes get committed. The conversation traces the idea's lineage from AlphaEvolve's evolutionary code loops through Yu's own SATLUTION and ABCEvo work, framing HORIZON as the next rung: evolving the hardware artifact itself rather than the tools used to build it. It contrasts HORIZON with two existing approaches to LLM-based RTL generation — domain-tuned one-shot generators like RTLCoder and ChipNeMo, and iterative repair systems like AutoChip and RTLFixer — and explains why hardware's unforgiving, concurrent, tape-out-or-bust nature makes "mostly correct" useless in a way it isn't for software. It also introduces CVDP, a 783-problem benchmark built to stress-test agentic and non-agentic Verilog generation now that older benchmarks are saturating. Listeners interested in whether AI coding-agent techniques can transfer to safety-critical, irreversible engineering domains will find the structural argument here more compelling than the raw benchmark numbers.

Sources:
1. Agentic Hardware Design as Repository-Level Code Evolution — Cunxi Yu, Chenhui Deng, Nathaniel Pinckney, Brucek Khailany, 2026
http://arxiv.org/abs/2606.28279v1
2. AlphaEvolve: A coding agent for scientific and algorithmic discovery — Novikov et al. (Google DeepMind), 2025
https://scholar.google.com/scholar?q=AlphaEvolve%3A+A+coding+agent+for+scientific+and+algorithmic+discovery
3. SATLUTION: scaling repository-level self-evolution to SAT solvers — Yu et al., 2025
https://scholar.google.com/scholar?q=SATLUTION%3A+scaling+repository-level+self-evolution+to+SAT+solvers
4. ABCEvo: self-evolving the ABC logic-synthesis system — Yu et al., 2026
https://scholar.google.com/scholar?q=ABCEvo%3A+self-evolving+the+ABC+logic-synthesis+system
5. SWE-agent: Agent-Computer Interfaces Enable Automated Software Engineering — Yang et al., 2024
https://scholar.google.com/scholar?q=SWE-agent%3A+Agent-Computer+Interfaces+Enable+Automated+Software+Engineering
6. VeriGen: A Large Language Model for Verilog Code Generation — Thakur et al., 2024
https://scholar.google.com/scholar?q=VeriGen%3A+A+Large+Language+Model+for+Verilog+Code+Generation
7. RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation — Liu et al., 2025
https://scholar.google.com/scholar?q=RTLCoder%3A+Fully+Open-Source+and+Efficient+LLM-Assisted+RTL+Code+Generation
8. ChipNeMo: Domain-Adapted LLMs for Chip Design — Liu et al., 2023
https://scholar.google.com/scholar?q=ChipNeMo%3A+Domain-Adapted+LLMs+for+Chip+Design
9. CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations — Liu et al., 2024
https://scholar.google.com/scholar?q=CraftRTL%3A+High-quality+Synthetic+Data+Generation+for+Verilog+Code+Models+with+Correct-by-Construction+Non-Textual+Representations
10. Autonomous Code Evolution Meets NP-Completeness (SATLUTION) — Yu, Liang, Ho, Ren, 2025
https://scholar.google.com/scholar?q=Autonomous+Code+Evolution+Meets+NP-Completeness+%28SATLUTION%29
11. Autonomous Evolution of EDA Tools: Multi-Agent Self-Evolved ABC (ABCEvo) — Yu, Liang, Ho, Ren, 2026
https://scholar.google.com/scholar?q=Autonomous+Evolution+of+EDA+Tools%3A+Multi-Agent+Self-Evolved+ABC+%28ABCEvo%29
12. Comprehensive Verilog Design Problems (CVDP) — Pinckney, Deng, Ho, Tsai, Liu, Zhou, Khailany, Ren, 2025
https://scholar.google.com/scholar?q=Comprehensive+Verilog+Design+Problems+%28CVDP%29
13. SWE-bench: Can Language Models Resolve Real-World GitHub Issues? / SWE-Bench+ / 'Are Solved Issues in SWE-bench Really Solved Correctly?' — Jimenez et al. (2024); Aleithan et al. (2024); Wang, Pradel, Liu (2026), 2024–2026
https://scholar.google.com/scholar?q=SWE-bench%3A+Can+Language+Models+Resolve+Real-World+GitHub+Issues%3F+%2F+SWE-Bench%2B+%2F+%27Are+Solved+Issues+in+SWE-bench+Really+Solved+Correctly%3F%27
14. ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs / MAGE: A Multi-Agent Engine for Automated RTL Code Generation — Deng, Yu, Liu, Pinckney, Khailany, Ren (2026); Zhao, Zhang, Huang, Yu, Zhao (2025), 2026 / 2025
https://scholar.google.com/scholar?q=ACE-RTL%3A+When+Agentic+Context+Evolution+Meets+RTL-Specialized+LLMs+%2F+MAGE%3A+A+Multi-Agent+Engine+for+Automated+RTL+Code+Generation